EP3SE260H780C2N vs EP3SE260H780C3N Сравнение
Подробное сравнение бок о бок EP3SE260H780C2N от Intel и EP3SE260H780C3N от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Intel
EP3SE260H780C2N - Stratix III E FPGA 255K LE, 780-BGA | Intel
EP3SE260H780C2N ⚠ Последняя закупкаIntel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ АктивенСравнение характеристик
| Параметр | EP3SE260H780C2N | EP3SE260H780C3N |
|---|---|---|
| Бренд | Intel | Intel |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Последняя закупка | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $3.600,00 | $1.325,00 |
| Series | Stratix III E | Stratix® III E |
| Logic Elements | 255,000 | — |
| LABs / CLBs | 10,200 | — |
| Total RAM Bits | 16,672,768 | — |
| User I/O Count | 488 | — |
| Number of Transceivers | [DATA_NEEDED: transceiver count] | — |
| Core Voltage | 0.9 V | — |
| Корпус | 780-BGA FCBGA | 780-BBGA, FCBGA (H780) |
| Тип монтажа | Surface Mount | Surface Mount |
| Диапазон рабочих температур | Commercial (0C to +85C) | — |
| Speed Grade | C2 | — |
| Уровень MSL | 3 (168 hours) | — |
| Reflow Peak Time Max | 40 s | — |
| Статус RoHS | [DATA_NEEDED: rohs status] | Compliant (lead-free 'N' suffix) |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Package Code | BGA | — |
| Terminal Form | Ball | — |
| Number of Terminals | 780 | — |
| Process Node | 40 nm | — |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| User I/Os | — | 488 |
| Number of Pins / Balls | — | 780 |
| Рабочая температура | — | 0 °C to +85 °C (C grade, commercial) |
| Process Technology | — | 40 nm CMOS |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Уровень чувствительности к влаге (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |