EP3SE260H780C2N vs EP3SE260H780C3N Comparaison
Comparaison détaillée côte à côte de EP3SE260H780C2N par Intel et EP3SE260H780C3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ ActifComparaison des spécifications
| Paramètre | EP3SE260H780C2N | EP3SE260H780C3N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3 600,00 | $1 325,00 |
| Series | Stratix III E | Stratix® III E |
| Logic Elements | 255,000 | — |
| LABs / CLBs | 10,200 | — |
| Total RAM Bits | 16,672,768 | — |
| User I/O Count | 488 | — |
| Number of Transceivers | [DATA_NEEDED: transceiver count] | — |
| Core Voltage | 0.9 V | — |
| Boîtier | 780-BGA FCBGA | 780-BBGA, FCBGA (H780) |
| Type de montage | Surface Mount | Surface Mount |
| Plage de température de fonctionnement | Commercial (0C to +85C) | — |
| Speed Grade | C2 | — |
| Niveau MSL | 3 (168 hours) | — |
| Reflow Peak Time Max | 40 s | — |
| Statut RoHS | [DATA_NEEDED: rohs status] | Compliant (lead-free 'N' suffix) |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Package Code | BGA | — |
| Terminal Form | Ball | — |
| Number of Terminals | 780 | — |
| Process Node | 40 nm | — |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| User I/Os | — | 488 |
| Number of Pins / Balls | — | 780 |
| Température de fonctionnement | — | 0 °C to +85 °C (C grade, commercial) |
| Process Technology | — | 40 nm CMOS |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Niveau de sensibilité à l'humidité (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |