EP610LC-30 vs EP610LC15 Vergleich
Detaillierter Direktvergleich von EP610LC-30 von Intel und EP610LC15 von Rochester Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
EP610LC15 ObsoleteSpezifikationsvergleich
| Parameter | EP610LC-30 | EP610LC15 |
|---|---|---|
| Marke | Intel | Rochester Electronics |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,40 | $5,45 |
| Family | Classic EPLD (EP610) | — |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (±10%) |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | UV-erasable EPROM, CMOS |
| Gehäuse | 24-pin CERDIP / PDIP | PLCC-28 (J-Lead) |
| Betriebstemperatur | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0 °C to +70 °C (LC suffix = commercial) |
| Erase/Program Cycles | 1000 typical | — |
| Montageart | Through-Hole | — |
| Ausgangstyp | CMOS tri-state (programmable) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant (Rochester re-creation) |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Device Family | — | Classic EPLD (EP610) |
| Number of Macrocells | — | 16 |
| Number of Usable Gates | — | [DATA_NEEDED: usable gate count] |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Toggle Frequency (fMAX) | — | 83.3 MHz |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 16 |
| Total Logic Pins | — | 24 |
| Programming Interface | — | Altera 4-pin serial (Classic algorithm) |
| Security Bit | — | Yes (programmable) |