EP610LC-30 vs EP610LC15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-30 sa pamamagitan ng Intel at EP610LC15 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
EP610LC15 ObsoletePagsanggunian na paghahambing
| Parametro | EP610LC-30 | EP610LC15 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD (EP610) | — |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (±10%) |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | UV-erasable EPROM, CMOS |
| Packhaging | 24-pin CERDIP / PDIP | PLCC-28 (J-Lead) |
| Temperature na Operasyon | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0 °C to +70 °C (LC suffix = commercial) |
| Erase/Program Cycles | 1000 typical | — |
| Uri ng Pagpapasok | Through-Hole | — |
| Type ng Output | CMOS tri-state (programmable) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (Rochester re-creation) |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Device Family | — | Classic EPLD (EP610) |
| Number of Macrocells | — | 16 |
| Number of Usable Gates | — | [DATA_NEEDED: usable gate count] |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Toggle Frequency (fMAX) | — | 83.3 MHz |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 16 |
| Total Logic Pins | — | 24 |
| Programming Interface | — | Altera 4-pin serial (Classic algorithm) |
| Security Bit | — | Yes (programmable) |