EP610LC-30 vs EP610LC15 比較
詳細並排比較 EP610LC-30 由 Intel 與 EP610LC15 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
EP610LC15 Obsolete規格比較
| 參數 | EP610LC-30 | EP610LC15 |
|---|---|---|
| 品牌 | Intel | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP610) | — |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (±10%) |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | UV-erasable EPROM, CMOS |
| 封裝 | 24-pin CERDIP / PDIP | PLCC-28 (J-Lead) |
| 工作溫度 | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0 °C to +70 °C (LC suffix = commercial) |
| Erase/Program Cycles | 1000 typical | — |
| 安裝類型 | Through-Hole | — |
| 輸出類型 | CMOS tri-state (programmable) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant (Rochester re-creation) |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Device Family | — | Classic EPLD (EP610) |
| Number of Macrocells | — | 16 |
| Number of Usable Gates | — | [DATA_NEEDED: usable gate count] |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Toggle Frequency (fMAX) | — | 83.3 MHz |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 16 |
| Total Logic Pins | — | 24 |
| Programming Interface | — | Altera 4-pin serial (Classic algorithm) |
| Security Bit | — | Yes (programmable) |