EP610LC-35 vs EP610JI-30 Vergleich
Detaillierter Direktvergleich von EP610LC-35 von Altera und EP610JI-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610LC-35 | EP610JI-30 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $9,40 |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP610) |
| Device Series | EP610 | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 37 ns | 30 ns (max) |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | — |
| Gehäuse | 28-pin PLCC (J-lead) | CQCC28 (windowed ceramic JLCC, J-bend) |
| Betriebstemperatur | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | -40C to +85C (industrial, per EP610 family suffix convention) |
| Speed Grade | -35 (slowest EP610) | — |
| Montageart | Surface Mount | Surface Mount (JLCC) |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| RoHS-Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead_free] | [DATA_NEEDED: lead-free status] |
| MSL-Level | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Pipelined Data Rate | — | Up to 100 MHz |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| External Clocks | — | 2 |
| Versorgungsspannung | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Package Code | — | JLCC-28 / CQCC28 |
| Erasure Method | — | Ultraviolet (UV) via top window |
| Programming | — | Altera Logic Programmer compatible |