EP610LC-35 vs EP610JI-30 对比
详细并排对比 EP610LC-35 出自 Altera 和 EP610JI-30 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610LC-35 | EP610JI-30 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $9.40 |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP610) |
| Device Series | EP610 | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 37 ns | 30 ns (max) |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | — |
| 封装 | 28-pin PLCC (J-lead) | CQCC28 (windowed ceramic JLCC, J-bend) |
| 工作温度 | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | -40C to +85C (industrial, per EP610 family suffix convention) |
| Speed Grade | -35 (slowest EP610) | — |
| 安装类型 | Surface Mount | Surface Mount (JLCC) |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| RoHS 状态 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead_free] | [DATA_NEEDED: lead-free status] |
| MSL 等级 | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Pipelined Data Rate | — | Up to 100 MHz |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| External Clocks | — | 2 |
| 电源电压 | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Package Code | — | JLCC-28 / CQCC28 |
| Erasure Method | — | Ultraviolet (UV) via top window |
| Programming | — | Altera Logic Programmer compatible |