EP910DC-35 vs EP910DC-40 Vergleich

Detaillierter Direktvergleich von EP910DC-35 von Altera und EP910DC-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DC-35 EP910DC-40
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,95 $13,95
Device Type UV-Erasable CMOS PLD (PAL-type) —
Family Classic EPLD EP910 —
Architecture PAL-type sum-of-products AND-OR array PAL-type AND/OR, UV-erasable CMOS
Usable Gates 900 gates —
Macrocells 24 24
Product Terms 240 240 maximum
Dedicated Inputs 12 12
I/O Pins 24 —
Total Inputs 36 —
Propagation Delay (tpd) 35 ns —
Maximale Taktfrequenz 37 MHz (typical, internal) —
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) —
Betriebstemperatur 0 °C to +70 °C (commercial) —
Gehäuse 40-pin CDIP (Ceramic DIP) with quartz window DIP-40 (ceramic, through-hole)
Lead Pitch 2.540 mm —
Termination Style Through-Hole —
Programming Method JEDEC fuse map via device programmer; UV erase UV-erase + EPROM programmer; on-board logic test circuitry
Technology CMOS, UV-erasable EPROM cell —
RoHS-Status Non-compliant (ceramic DIP with Pb-bearing lead finish) [DATA_NEEDED: rohs_status]
Lifecycle Obsolete / last-time-buy from authorized distributors —
Device Family — Classic EPLD (EP910 series)
Bidirectional I/O Pins — 24
Total Inputs to Logic Array — 36
Maximum Propagation Delay (tPD) — 40 ns
Maximum Operating Frequency (fMAX) — 25 MHz
Global Clocks — 2
Versorgungsspannung — 5 V (typical for Classic EPLD family)
Operating Temperature (Commercial) — 0 °C to 70 °C
Montageart — Through-Hole

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