EP910DC-35 vs EP910DC-40 비교
다음의 상세 나란히 비교: EP910DC-35 제조: Altera 및 EP910DC-40 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910DC-35 | EP910DC-40 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $10.95 | $13.95 |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | — |
| Family | Classic EPLD EP910 | — |
| Architecture | PAL-type sum-of-products AND-OR array | PAL-type AND/OR, UV-erasable CMOS |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | 240 maximum |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| 최대 클록 주파수 | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| 동작 온도 | 0 °C to +70 °C (commercial) | — |
| 패키지 | 40-pin CDIP (Ceramic DIP) with quartz window | DIP-40 (ceramic, through-hole) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | UV-erase + EPROM programmer; on-board logic test circuitry |
| Technology | CMOS, UV-erasable EPROM cell | — |
| RoHS 상태 | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: rohs_status] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| 공급 전압 | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| 실장 유형 | — | Through-Hole |