EP910DC-35 vs EP910DC-40 对比
详细并排对比 EP910DC-35 出自 Altera 和 EP910DC-40 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910DC-35 | EP910DC-40 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.95 | $13.95 |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | — |
| Family | Classic EPLD EP910 | — |
| Architecture | PAL-type sum-of-products AND-OR array | PAL-type AND/OR, UV-erasable CMOS |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | 240 maximum |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| 最大时钟频率 | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作温度 | 0 °C to +70 °C (commercial) | — |
| 封装 | 40-pin CDIP (Ceramic DIP) with quartz window | DIP-40 (ceramic, through-hole) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | UV-erase + EPROM programmer; on-board logic test circuitry |
| Technology | CMOS, UV-erasable EPROM cell | — |
| RoHS 状态 | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: rohs_status] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| 电源电压 | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| 安装类型 | — | Through-Hole |