EP910LC-32 vs EP910LC-30Y Vergleich

Detaillierter Direktvergleich von EP910LC-32 von Altera und EP910LC-30Y von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910LC-32 EP910LC-30Y
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,85 $25,40
Device Family Altera Classic EPLD —
Number of Macrocells 24 —
Number of Usable Gates 900 gates (typical) —
Number of Dedicated Inputs 10 —
Number of I/O Pins 20 —
Gehäuse PLCC-32 PLCC-44
Speed Grade -32 —
Maximum Toggle Frequency (fMAX) [DATA_NEEDED: fMAX value in MHz for -32 grade] —
Pin-to-Pin Propagation Delay (tPD) [DATA_NEEDED: tPD in ns for -32 grade] —
Supply Voltage (VCC) 5 V —
Logic Family Low-power CMOS (LC suffix) —
Programming Method UV-erasable or one-time programmable (OTP for LC windowless variant) —
Betriebstemperaturbereich [DATA_NEEDED: commercial or industrial grade] —
I/O Standard TTL-compatible —
Montageart Surface Mount (PLCC socket or direct solder) Surface Mount (PLCC socket)
RoHS-Status unknown [DATA_NEEDED: RoHS status not specified in retrieved data]
MSL-Level unknown —
Family — Altera Classic EPLD
Device Type — EPLD (Erasable Programmable Logic Device)
Macrocells — 24
Usable Gates — 450
Pin-to-Pin Delay (tPD) — 30 ns
Counter Frequency (fMAX) — 100 MHz (family maximum)
Versorgungsspannung — 5 V (TTL-compatible)
Process Technology — CMOS, UV-erasable / OTP
Betriebstemperatur — Commercial 0C to +70C
Speed/Power Grade — LC (low-power, 30ns)
Processing Flow — Y (extended reliability)
Logic Compatibility — 100% TTL emulation

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