EP910LC-32 vs EP910LC-30Y Comparison
Detailed side-by-side comparison of EP910LC-32 by Altera and EP910LC-30Y by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-32 | EP910LC-30Y |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Device Family | Altera Classic EPLD | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | 900 gates (typical) | — |
| Number of Dedicated Inputs | 10 | — |
| Number of I/O Pins | 20 | — |
| Package | PLCC-32 | PLCC-44 |
| Speed Grade | -32 | — |
| Maximum Toggle Frequency (fMAX) | [DATA_NEEDED: fMAX value in MHz for -32 grade] | — |
| Pin-to-Pin Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns for -32 grade] | — |
| Supply Voltage (VCC) | 5 V | — |
| Logic Family | Low-power CMOS (LC suffix) | — |
| Programming Method | UV-erasable or one-time programmable (OTP for LC windowless variant) | — |
| Operating Temperature Range | [DATA_NEEDED: commercial or industrial grade] | — |
| I/O Standard | TTL-compatible | — |
| Mounting Type | Surface Mount (PLCC socket or direct solder) | Surface Mount (PLCC socket) |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status not specified in retrieved data] |
| MSL Level | unknown | — |
| Family | — | Altera Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Counter Frequency (fMAX) | — | 100 MHz (family maximum) |
| Supply Voltage | — | 5 V (TTL-compatible) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Operating Temperature | — | Commercial 0C to +70C |
| Speed/Power Grade | — | LC (low-power, 30ns) |
| Processing Flow | — | Y (extended reliability) |
| Logic Compatibility | — | 100% TTL emulation |