EP910LC-32 vs EP910LC-30Y 对比

详细并排对比 EP910LC-32 出自 Altera 和 EP910LC-30Y 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910LC-32 EP910LC-30Y
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $9.85 $25.40
Device Family Altera Classic EPLD —
Number of Macrocells 24 —
Number of Usable Gates 900 gates (typical) —
Number of Dedicated Inputs 10 —
Number of I/O Pins 20 —
封装 PLCC-32 PLCC-44
Speed Grade -32 —
Maximum Toggle Frequency (fMAX) [DATA_NEEDED: fMAX value in MHz for -32 grade] —
Pin-to-Pin Propagation Delay (tPD) [DATA_NEEDED: tPD in ns for -32 grade] —
Supply Voltage (VCC) 5 V —
Logic Family Low-power CMOS (LC suffix) —
Programming Method UV-erasable or one-time programmable (OTP for LC windowless variant) —
工作温度范围 [DATA_NEEDED: commercial or industrial grade] —
I/O Standard TTL-compatible —
安装类型 Surface Mount (PLCC socket or direct solder) Surface Mount (PLCC socket)
RoHS 状态 unknown [DATA_NEEDED: RoHS status not specified in retrieved data]
MSL 等级 unknown —
Family — Altera Classic EPLD
Device Type — EPLD (Erasable Programmable Logic Device)
Macrocells — 24
Usable Gates — 450
Pin-to-Pin Delay (tPD) — 30 ns
Counter Frequency (fMAX) — 100 MHz (family maximum)
电源电压 — 5 V (TTL-compatible)
Process Technology — CMOS, UV-erasable / OTP
工作温度 — Commercial 0C to +70C
Speed/Power Grade — LC (low-power, 30ns)
Processing Flow — Y (extended reliability)
Logic Compatibility — 100% TTL emulation

数据手册与资源

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