EP910PI-20 vs EP910PI-30T Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PI-20 disebabkan oleh Altera dan EP910PI-30T disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910PI-20 | EP910PI-30T |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 20 ns | 30 ns |
| Kemasan | PDIP-40 (PI suffix) | — |
| Jenis Pemasangan | Through-Hole | Through-Hole |
| Supply Voltage (VCC) | 5 V (+/- 5%) | 4.75 V to 5.25 V (5 V nominal) |
| Suhu Operasi | -40C to +85C (industrial) | -40 C to +85 C (industrial) |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | CMOS, UV-erasable (windowed ceramic) |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | — |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Pins | 24 | — |
| Maximum Counter Frequency | 125 MHz | — |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | — |
| Programmable Polarity | Yes (XOR gate per macrocell) | — |
| Macrocell Flip-Flop | Yes (D-type, programmable) | — |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | — |
| Programming Interface | JEDEC file via Altera programming hardware | — |
| Status RoHS | unknown | [DATA_NEEDED: RoHS status] |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 480 |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Programming | — | Altera Classic device programmer / MAX+PLUS II flow |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |