EP910PI-25 vs EP910PI-12T Vergleich
Detaillierter Direktvergleich von EP910PI-25 von Intel und EP910PI-12T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PI-25 | EP910PI-12T |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,95 | $9,95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 40 MHz | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V (4.75 V min, 5.25 V max) |
| Process Technology | 5 V CMOS (EPROM-based) | CMOS |
| Gehäuse | PDIP-40 (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| Pin-Anzahl | 40 | — |
| Montageart | Through-Hole | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmability | UV-erasable (windowed) / one-time-programmable | — |
| RoHS-Status | Non-compliant (PDIP package) | Non-compliant (legacy PDIP package, contains lead) |
| Propagation Delay (tPD) | — | 12 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Logic Gates | — | [DATA_NEEDED: logic gate count] |
| External Clock Inputs | — | 2 |
| Outputs | — | 24 |
| Terminals / Pin Count | — | 44 (PDIP-40 package pinout with NC pins) |
| Programmable Technology | — | UV-erasable EPROM |
| Programming Interface | — | JEDEC-standard |
| Lebenszyklusstatus | — | NRND / EOL (mature legacy product) |