EP910PI-25 vs EP910PI-12T Comparación
Comparación detallada lado a lado de EP910PI-25 por Intel y EP910PI-12T por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PI-25 | EP910PI-12T |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,95 | $9,95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 40 MHz | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V (4.75 V min, 5.25 V max) |
| Process Technology | 5 V CMOS (EPROM-based) | CMOS |
| Encapsulado | PDIP-40 (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| Recuento de pines | 40 | — |
| Tipo de montaje | Through-Hole | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmability | UV-erasable (windowed) / one-time-programmable | — |
| Estado RoHS | Non-compliant (PDIP package) | Non-compliant (legacy PDIP package, contains lead) |
| Propagation Delay (tPD) | — | 12 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Logic Gates | — | [DATA_NEEDED: logic gate count] |
| External Clock Inputs | — | 2 |
| Outputs | — | 24 |
| Terminals / Pin Count | — | 44 (PDIP-40 package pinout with NC pins) |
| Programmable Technology | — | UV-erasable EPROM |
| Programming Interface | — | JEDEC-standard |
| Estado del ciclo de vida | — | NRND / EOL (mature legacy product) |