EPC1064VLC20 vs EPC2LC20 Vergleich

Detaillierter Direktvergleich von EPC1064VLC20 von Altera und EPC2LC20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPC1064VLC20 EPC2LC20
Marke Altera Altera
Kategorie Memory ICs Memory ICs
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $1,51 $7,20
Speichertyp OTP (One-Time Programmable) Configuration PROM Non-volatile configuration PROM
Speichergröße 65,536 bit (64 Kb) 1.6 Mbit
Speicherorganisation 64K x 1 (serial) —
Schnittstelle Serial, daisy-chain capable —
Supply Voltage (VCC) 4.75 V to 5.25 V (5.0 V nominal) —
Programmable Type OTP (factory programmed; not in-system programmable) —
Gehäuse 20-pin PLCC (J-lead, 9 x 9 mm) 20-pin PLCC (J-lead, 9x9 mm)
Betriebstemperatur 0C to +70C (commercial) -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Compatible FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX —
Cascade Support Yes, daisy-chain output for up to 8 devices Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Montageart Surface Mount (PLCC socket compatible) Surface Mount
RoHS-Status [DATA_NEEDED: RoHS compliance] Non-Compliant (original Altera Pb-containing part)
Lead-Free [DATA_NEEDED: lead-free status] —
MSL-Level [DATA_NEEDED: MSL rating] —
Programming Method Altera programming hardware (factory, pre-solder) —
Configuration Interface — Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Programming Interface — IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC — 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range — 5.0 V or 3.3 V
Supported FPGA Families — ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
Lead-Free Version — EPC2LC20N available as lead-free equivalent
Programming Support — Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan — IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

Datenblätter & Ressourcen

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