EPC1064VLC20 vs EPC2LC20 比較
詳細な並列比較: EPC1064VLC20 メーカー: Altera および EPC2LC20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC1064VLC20 | EPC2LC20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | Memory ICs | Memory ICs |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1.51 | $7.20 |
| メモリタイプ | OTP (One-Time Programmable) Configuration PROM | Non-volatile configuration PROM |
| メモリサイズ | 65,536 bit (64 Kb) | 1.6 Mbit |
| メモリ構成 | 64K x 1 (serial) | — |
| インターフェース | Serial, daisy-chain capable | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Programmable Type | OTP (factory programmed; not in-system programmable) | — |
| パッケージ | 20-pin PLCC (J-lead, 9 x 9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| 動作温度 | 0C to +70C (commercial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Compatible FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Cascade Support | Yes, daisy-chain output for up to 8 devices | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Programming Method | Altera programming hardware (factory, pre-solder) | — |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |