EPC16SI16N vs EPC16QC100DM Vergleich
Detaillierter Direktvergleich von EPC16SI16N von Intel und EPC16QC100DM von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EPC16SI16N | EPC16QC100DM |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,35 | $15,85 |
| Speichertyp | Non-volatile flash (enhanced configuration device) | Non-volatile Configuration PROM (NOR flash) |
| Speichergröße | 16 Mb (16,777,216 bits) | — |
| Schnittstelle | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) | — |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| Maximum Operating Frequency | 40 MHz (fast configuration mode) | — |
| Betriebsversorgungsspannung | 3.3 V (typ) | — |
| Betriebstemperatur | -40 C to +85 C (industrial, 'SI' suffix) | — |
| Gehäuse | 16-pin SOIC (300 mil, 'SI' suffix) | 100-pin PQFP (QFPA) |
| Montageart | Surface Mount | — |
| Lead-Free / Finish | Lead-free (matte tin), 'N' suffix | — |
| MSL-Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| RoHS-Status | Compliant | — |
| In-System Programmability | Yes (via JTAG, multiple reprogramming cycles) | — |
| Compatible FPGA Series | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III | — |
| Configuration Daisy-Chaining | Supported (multiple devices / multiple FPGAs) | — |
| On-Chip Charge Pump | Integrated (no external VPP required) | — |
| Memory Density | — | 16 Mbit (2 Mbyte) |
| Configuration Interface | — | Serial (SPI-compatible, Altera FPP mode) |
| Core Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| I/O Voltage (VIO) | — | 2.5 V / 3.3 V selectable |
| Output Voltage (VPP) | — | 1.8 V / 2.5 V / 3.3 V selectable |
| Maximum DCLK Frequency | — | 40 MHz |
| Cascadable | — | Yes (multi-device daisy chain via nCASC) |
| In-System Programming | — | Yes (IEEE 1532 / JTAG) |
| Program/Erase Cycles | — | [DATA_NEEDED: program/erase cycle endurance] |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Betriebstemperaturbereich | — | -40 C to +85 C (industrial) |
| Package Code | — | Q100 + DM suffix |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Compatible FPGA Families | — | Stratix, Cyclone, APEX, ACEX |