EPC16SI16N vs EPC16QC100DM 对比

详细并排对比 EPC16SI16N 出自 Intel 和 EPC16QC100DM 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC16SI16N EPC16QC100DM
品牌 Intel Intel
分类 FPGA & CPLD Memory ICs
生命周期状态 最后采购期 不推荐新设计
库存状态 有库存 有库存
单价(USD) $4.35 $15.85
存储器类型 Non-volatile flash (enhanced configuration device) Non-volatile Configuration PROM (NOR flash)
存储容量 16 Mb (16,777,216 bits) —
接口 Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) —
Programming Interface JTAG (IEEE 1149.1 boundary scan) —
Maximum Operating Frequency 40 MHz (fast configuration mode) —
工作电源电压 3.3 V (typ) —
工作温度 -40 C to +85 C (industrial, 'SI' suffix) —
封装 16-pin SOIC (300 mil, 'SI' suffix) 100-pin PQFP (QFPA)
安装类型 Surface Mount —
Lead-Free / Finish Lead-free (matte tin), 'N' suffix —
MSL 等级 [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL rating]
RoHS 状态 Compliant —
In-System Programmability Yes (via JTAG, multiple reprogramming cycles) —
Compatible FPGA Series Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III —
Configuration Daisy-Chaining Supported (multiple devices / multiple FPGAs) —
On-Chip Charge Pump Integrated (no external VPP required) —
Memory Density — 16 Mbit (2 Mbyte)
Configuration Interface — Serial (SPI-compatible, Altera FPP mode)
Core Supply Voltage (VCC) — 3.0 V to 3.6 V
I/O Voltage (VIO) — 2.5 V / 3.3 V selectable
Output Voltage (VPP) — 1.8 V / 2.5 V / 3.3 V selectable
Maximum DCLK Frequency — 40 MHz
Cascadable — Yes (multi-device daisy chain via nCASC)
In-System Programming — Yes (IEEE 1532 / JTAG)
Program/Erase Cycles — [DATA_NEEDED: program/erase cycle endurance]
Data Retention — [DATA_NEEDED: data retention years]
工作温度范围 — -40 C to +85 C (industrial)
Package Code — Q100 + DM suffix
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]
Compatible FPGA Families — Stratix, Cyclone, APEX, ACEX

数据手册与资源

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