EPC16SI16N vs EPC16QC100DM Comparación
Comparación detallada lado a lado de EPC16SI16N por Intel y EPC16QC100DM por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N ⚠ Última compra
Comparación de especificaciones
| Parámetro | EPC16SI16N | EPC16QC100DM |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | Memory ICs |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,35 | $15,85 |
| Tipo de memoria | Non-volatile flash (enhanced configuration device) | Non-volatile Configuration PROM (NOR flash) |
| Tamaño de memoria | 16 Mb (16,777,216 bits) | — |
| Interfaz | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) | — |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| Maximum Operating Frequency | 40 MHz (fast configuration mode) | — |
| Tensión de alimentación de funcionamiento | 3.3 V (typ) | — |
| Temperatura de funcionamiento | -40 C to +85 C (industrial, 'SI' suffix) | — |
| Encapsulado | 16-pin SOIC (300 mil, 'SI' suffix) | 100-pin PQFP (QFPA) |
| Tipo de montaje | Surface Mount | — |
| Lead-Free / Finish | Lead-free (matte tin), 'N' suffix | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Estado RoHS | Compliant | — |
| In-System Programmability | Yes (via JTAG, multiple reprogramming cycles) | — |
| Compatible FPGA Series | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III | — |
| Configuration Daisy-Chaining | Supported (multiple devices / multiple FPGAs) | — |
| On-Chip Charge Pump | Integrated (no external VPP required) | — |
| Memory Density | — | 16 Mbit (2 Mbyte) |
| Configuration Interface | — | Serial (SPI-compatible, Altera FPP mode) |
| Core Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| I/O Voltage (VIO) | — | 2.5 V / 3.3 V selectable |
| Output Voltage (VPP) | — | 1.8 V / 2.5 V / 3.3 V selectable |
| Maximum DCLK Frequency | — | 40 MHz |
| Cascadable | — | Yes (multi-device daisy chain via nCASC) |
| In-System Programming | — | Yes (IEEE 1532 / JTAG) |
| Program/Erase Cycles | — | [DATA_NEEDED: program/erase cycle endurance] |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Rango de temperatura de funcionamiento | — | -40 C to +85 C (industrial) |
| Package Code | — | Q100 + DM suffix |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Compatible FPGA Families | — | Stratix, Cyclone, APEX, ACEX |