EPC22C20N vs EPC2CC20N Vergleich
Detaillierter Direktvergleich von EPC22C20N von Altera und EPC2CC20N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC22C20N | EPC2CC20N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $11,40 | $10,85 |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | Configuration PROM for SRAM-based LUT FPGAs | — |
| Target FPGA Family | FLEX 10K, FLEX 6000, APEX 20K series | — |
| Configuration Interface | Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) | 16-bit parallel (FPP) / Passive Serial (PS) |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster |
| Versorgungsspannung | 3.3 V or 5 V | — |
| Gehäuse | 20-pin PLCC (J-lead) | PLCC-20 |
| Package Marking Code | EPC22C20N | — |
| Pin-Anzahl | 20 | — |
| Montageart | Surface Mount / Socket | Surface Mount (PLCC-20 socket compatible) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temp range] |
| Bitstream Capacity | [DATA_NEEDED: bitstream capacity in bits] | — |
| Configuration Time | [DATA_NEEDED: typical configuration time] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Lebenszyklusstatus | Obsolete (last-time-buy from Altera announced for legacy configuration devices) | — |
| Funktion | — | Configuration device for SRAM-based LUT FPGAs |
| Density | — | [DATA_NEEDED: bitstream density in bits] |
| Supply Voltage (VCC) | — | 3.3 V |
| In-System Programmable | — | Yes |
| Error Detection | — | 16-bit CRC on configuration frames |
| Configuration Modes Supported | — | FPP and PS (depends on host FPGA) |
| Cascadable | — | Yes (multiple EPC2 devices for larger bitstreams) |
| Open-Drain Status Pin | — | Yes (CONF_DONE / nSTATUS compatible) |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |