EPC22C20N vs EPC2CC20N Comparação
Comparação detalhada lado a lado de EPC22C20N por Altera e EPC2CC20N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPC22C20N | EPC2CC20N |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | Memory ICs | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $11,40 | $10,85 |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | Configuration PROM for SRAM-based LUT FPGAs | — |
| Target FPGA Family | FLEX 10K, FLEX 6000, APEX 20K series | — |
| Configuration Interface | Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) | 16-bit parallel (FPP) / Passive Serial (PS) |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster |
| Tensão de alimentação | 3.3 V or 5 V | — |
| Encapsulamento | 20-pin PLCC (J-lead) | PLCC-20 |
| Package Marking Code | EPC22C20N | — |
| Contagem de pinos | 20 | — |
| Tipo de montagem | Surface Mount / Socket | Surface Mount (PLCC-20 socket compatible) |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temp range] |
| Bitstream Capacity | [DATA_NEEDED: bitstream capacity in bits] | — |
| Configuration Time | [DATA_NEEDED: typical configuration time] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Status do ciclo de vida | Obsolete (last-time-buy from Altera announced for legacy configuration devices) | — |
| Função | — | Configuration device for SRAM-based LUT FPGAs |
| Density | — | [DATA_NEEDED: bitstream density in bits] |
| Supply Voltage (VCC) | — | 3.3 V |
| In-System Programmable | — | Yes |
| Error Detection | — | 16-bit CRC on configuration frames |
| Configuration Modes Supported | — | FPP and PS (depends on host FPGA) |
| Cascadable | — | Yes (multiple EPC2 devices for larger bitstreams) |
| Open-Drain Status Pin | — | Yes (CONF_DONE / nSTATUS compatible) |
| Nível MSL | — | [DATA_NEEDED: MSL rating] |