EPC2C20 vs EPC2LI20NGA Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2C20 sa pamamagitan ng Altera at EPC2LI20NGA sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2C20 | EPC2LI20NGA |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Manufacturer | Altera | Altera / Intel PSG |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Packhaging | [DATA_NEEDED: package] | 20-PLCC (9x9 mm) |
| Bilang ng Pin | [DATA_NEEDED: pin count] | — |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (lead-free 'G' suffix) |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Laki ng Memory | — | 1.6 Mbit |
| Fungsi | — | In-System Programmable Configuration PROM |
| Target Device | — | SRAM-based LUT FPGAs |
| Volte ng Pagbibigay | — | 3.0 V to 3.6 V (3.3 V typical) |
| Configuration Interface | — | Passive Serial / Passive Parallel |
| Programming Method | — | In-System via JTAG (IEEE 1149.1) |
| Cascadable | — | Yes (DATA, DCLK chain) |
| Uri ng Pagpapasok | — | Surface Mount / Thru-Hole Socket |
| Lead-Free Termination | — | Yes (NiPdAu) |
| Process Technology | — | CMOS EEPROM |
| Datasheet Document | — | EPC2 datasheet (Altera) |