EPC2L120 vs EPC2L120N Vergleich

Detaillierter Direktvergleich von EPC2L120 von Altera und EPC2L120N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPC2L120 EPC2L120N
Marke Altera Intel
Kategorie Memory ICs FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $5,20 $7,85
Speichertyp Configuration PROM (Flash-based) —
Density 120 Kbit —
Configuration Interface Serial, FPGA-targeted —
Operating Voltage 2.7 V to 3.6 V (3.3 V typ) —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Gehäuse PLCC-20 84-pin PLCC (J-Lead)
Compatible FPGAs Altera Cyclone, Cyclone II, APEX-series —
Betriebstemperatur -40 C to +85 C [DATA_NEEDED: industrial temp range]
CONF_DONE Output Open-drain, wire-OR capable —
Data Retention 20 years (per Altera datasheet family) —
Program/Erase Cycles 100 cycles minimum —
Montageart Surface Mount —
RoHS-Status unknown unknown
Lead-Free unknown —
Family EPC2 (Enhanced Configuration) EPC2 (Enhanced Configuration Device)
Device Type — Configuration Device for SRAM-based LUT FPGAs
Manufacturer — Intel (formerly Altera)
Memory Capacity — 165,888 bits (400,000 gates equivalent)
Operating Voltage (VCCIO) — 2.7 V to 3.6 V
5V Tolerance — Yes (5V-tolerant I/O)
Configuration Clock (FPP) — Up to 66 MHz
Configuration Clock (PS) — Up to 33 MHz
Internal Oscillator — 8 MHz with programmable divider
JTAG Interface — IEEE Std 1149.1 compliant, ISP support
Programming Cycles — 100,000 erase/program cycles
Sector Erase Time — [DATA_NEEDED: typical sector erase time]
Configuration Schemes — FPP, PS, JTAG, daisy chain
Supported FPGA Families — Cyclone, APEX, FLEX, Mercury, ACEX, Stratix

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