EPC2L120 vs EPC2L120N 比較
詳細な並列比較: EPC2L120 メーカー: Altera および EPC2L120N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC2L120 | EPC2L120N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | Memory ICs | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $5.20 | $7.85 |
| メモリタイプ | Configuration PROM (Flash-based) | — |
| Density | 120 Kbit | — |
| Configuration Interface | Serial, FPGA-targeted | — |
| Operating Voltage | 2.7 V to 3.6 V (3.3 V typ) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| パッケージ | PLCC-20 | 84-pin PLCC (J-Lead) |
| Compatible FPGAs | Altera Cyclone, Cyclone II, APEX-series | — |
| 動作温度 | -40 C to +85 C | [DATA_NEEDED: industrial temp range] |
| CONF_DONE Output | Open-drain, wire-OR capable | — |
| Data Retention | 20 years (per Altera datasheet family) | — |
| Program/Erase Cycles | 100 cycles minimum | — |
| 実装タイプ | Surface Mount | — |
| RoHS ステータス | unknown | unknown |
| Lead-Free | unknown | — |
| Family | EPC2 (Enhanced Configuration) | EPC2 (Enhanced Configuration Device) |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |
| Supported FPGA Families | — | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |