EPC2L120 vs EPC2L120N Comparison

Detailed side-by-side comparison of EPC2L120 by Altera and EPC2L120N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC2L120 EPC2L120N
Brand Altera Intel
Category Memory ICs FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.20 $7.85
Memory Type Configuration PROM (Flash-based) β€”
Density 120 Kbit β€”
Configuration Interface Serial, FPGA-targeted β€”
Operating Voltage 2.7 V to 3.6 V (3.3 V typ) β€”
In-System Programmability Yes (IEEE 1149.1 JTAG) β€”
Package PLCC-20 84-pin PLCC (J-Lead)
Compatible FPGAs Altera Cyclone, Cyclone II, APEX-series β€”
Operating Temperature -40 C to +85 C [DATA_NEEDED: industrial temp range]
CONF_DONE Output Open-drain, wire-OR capable β€”
Data Retention 20 years (per Altera datasheet family) β€”
Program/Erase Cycles 100 cycles minimum β€”
Mounting Type Surface Mount β€”
RoHS Status unknown unknown
Lead-Free unknown β€”
Family EPC2 (Enhanced Configuration) EPC2 (Enhanced Configuration Device)
Device Type β€” Configuration Device for SRAM-based LUT FPGAs
Manufacturer β€” Intel (formerly Altera)
Memory Capacity β€” 165,888 bits (400,000 gates equivalent)
Operating Voltage (VCCIO) β€” 2.7 V to 3.6 V
5V Tolerance β€” Yes (5V-tolerant I/O)
Configuration Clock (FPP) β€” Up to 66 MHz
Configuration Clock (PS) β€” Up to 33 MHz
Internal Oscillator β€” 8 MHz with programmable divider
JTAG Interface β€” IEEE Std 1149.1 compliant, ISP support
Programming Cycles β€” 100,000 erase/program cycles
Sector Erase Time β€” [DATA_NEEDED: typical sector erase time]
Configuration Schemes β€” FPP, PS, JTAG, daisy chain
Supported FPGA Families β€” Cyclone, APEX, FLEX, Mercury, ACEX, Stratix

Datasheets & Resources

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