EPC2LC02N vs EPC2L20N Vergleich
Detaillierter Direktvergleich von EPC2LC02N von Intel und EPC2L20N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2LC02N | EPC2L20N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3,40 | $17,20 |
| Device Type | Enhanced Configuration Device (Configuration PROM) | — |
| Memory Density | 1.6 Mbit | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Schnittstelle | Serial or Parallel FPGA configuration, JTAG (IEEE 1149.1) ISP | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Supported FPGA Families | APEX II, APEX 20K, ACEX 1K, FLEX 10K, Mercury, Stratix (partial) | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) |
| Configuration Mode | Serial / Parallel / Multi-device daisy-chain | — |
| Betriebstemperatur | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Gehäuse | 20-pin PLCC (Plastic Leaded Chip Carrier) | — |
| Package Code | L (PLCC-20, leaded) | — |
| Montageart | Surface Mount / Socket | Surface Mount (J-Lead PLCC) |
| JTAG Compliance | IEEE 1149.1 (TAP controller with 4-wire interface) | — |
| DC Input Voltage (absolute max) | -0.3 V to +7.0 V (transients to -2.0 V / +7.0 V for <20 ns) | — |
| Lead-Free / RoHS | Lead finish version dependent (Pb-free and SnPb variants exist) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | 3 (168 hours) |
| Programming Cycles | 100 typical (flash endurance, per datasheet) | — |
| Funktion | — | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs |
| Speichergröße | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage - VCCINT/VCCIO | — | 3.0 V to 3.6 V or 4.5 V to 5.5 V |
| Gehäuse / Bauform | — | 20-LCC (J-Lead), PLCC-20 |
| Packaging | — | Tube |
| Configuration Interface | — | Serial (Altera FPP / PS configuration scheme) |
| Cascade Support | — | Yes (multi-PROM chain via CE control) |
| Programming Method | — | In-system via 4-wire ISP / JTAG-style |
| Pin-Anzahl | — | 20 |
| Lead Finish | — | Matte Tin (Pb-free) |
| RoHS-Status | — | Compliant |