EPC2LC02N vs EPC2L20N Comparación
Comparación detallada lado a lado de EPC2LC02N por Intel y EPC2L20N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2LC02N | EPC2L20N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | Memory ICs |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $3,40 | $17,20 |
| Device Type | Enhanced Configuration Device (Configuration PROM) | — |
| Memory Density | 1.6 Mbit | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Interfaz | Serial or Parallel FPGA configuration, JTAG (IEEE 1149.1) ISP | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Supported FPGA Families | APEX II, APEX 20K, ACEX 1K, FLEX 10K, Mercury, Stratix (partial) | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) |
| Configuration Mode | Serial / Parallel / Multi-device daisy-chain | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Encapsulado | 20-pin PLCC (Plastic Leaded Chip Carrier) | — |
| Package Code | L (PLCC-20, leaded) | — |
| Tipo de montaje | Surface Mount / Socket | Surface Mount (J-Lead PLCC) |
| JTAG Compliance | IEEE 1149.1 (TAP controller with 4-wire interface) | — |
| DC Input Voltage (absolute max) | -0.3 V to +7.0 V (transients to -2.0 V / +7.0 V for <20 ns) | — |
| Lead-Free / RoHS | Lead finish version dependent (Pb-free and SnPb variants exist) | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | 3 (168 hours) |
| Programming Cycles | 100 typical (flash endurance, per datasheet) | — |
| Función | — | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs |
| Tamaño de memoria | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage - VCCINT/VCCIO | — | 3.0 V to 3.6 V or 4.5 V to 5.5 V |
| Encapsulado / Carcasa | — | 20-LCC (J-Lead), PLCC-20 |
| Packaging | — | Tube |
| Configuration Interface | — | Serial (Altera FPP / PS configuration scheme) |
| Cascade Support | — | Yes (multi-PROM chain via CE control) |
| Programming Method | — | In-system via 4-wire ISP / JTAG-style |
| Recuento de pines | — | 20 |
| Lead Finish | — | Matte Tin (Pb-free) |
| Estado RoHS | — | Compliant |