EPM5032DC-2 vs EPM5032DC Vergleich
Detaillierter Direktvergleich von EPM5032DC-2 von Altera und EPM5032DC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032DC-2 | EPM5032DC |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,75 | $10,40 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Usable Gates (typical) | 600 | — |
| Logic Array Blocks (LABs) | 4 | 1 |
| Gehäuse | 20-pin CDIP (Ceramic DIP) | DIP-24 (ceramic, windowed) |
| Speed Grade | -2 (tPD ~25 ns, commercial) | DC (commercial) |
| Configuration Memory | EPROM (one-time programmable per generation; UV-erasable variants exist) | EPROM (UV-erasable via package window) |
| Supply Voltage (VCC) | 5 V (single supply, +/-5%) | — |
| Betriebstemperatur | 0C to +70C (commercial grade) | 0C to +70C |
| Programmable Pins / I/O | 20 pins (JEDEC-standard 0.300" ceramic DIP) | — |
| Programming Interface | Altera ByteBlaster / parallel-port JTAG-style ISP | — |
| Interconnect | Programmable Interconnect Array (PIA) with deterministic timing | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] | [DATA_NEEDED: RoHS status] |
| Montageart | Through-Hole (DIP) | Through-hole (DIP) |
| MSL-Level | Not applicable (through-hole hermetic ceramic) | — |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Technology | — | Bipolar EPROM, UV-erasable |
| Programmable Logic Elements | — | AND array + fixed OR array per macrocell |
| Pin-Anzahl | — | 24 |
| Programming Tool | — | Altera MAX+PLUS II / A+PLUS legacy |
| Lebenszyklusstatus | — | Obsolete (mature legacy) |