EPM5032DC-2 vs EPM5032DC 比較
詳細な並列比較: EPM5032DC-2 メーカー: Altera および EPM5032DC メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032DC-2 | EPM5032DC |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.75 | $10.40 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Usable Gates (typical) | 600 | — |
| Logic Array Blocks (LABs) | 4 | 1 |
| パッケージ | 20-pin CDIP (Ceramic DIP) | DIP-24 (ceramic, windowed) |
| Speed Grade | -2 (tPD ~25 ns, commercial) | DC (commercial) |
| Configuration Memory | EPROM (one-time programmable per generation; UV-erasable variants exist) | EPROM (UV-erasable via package window) |
| Supply Voltage (VCC) | 5 V (single supply, +/-5%) | — |
| 動作温度 | 0C to +70C (commercial grade) | 0C to +70C |
| Programmable Pins / I/O | 20 pins (JEDEC-standard 0.300" ceramic DIP) | — |
| Programming Interface | Altera ByteBlaster / parallel-port JTAG-style ISP | — |
| Interconnect | Programmable Interconnect Array (PIA) with deterministic timing | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] | [DATA_NEEDED: RoHS status] |
| 実装タイプ | Through-Hole (DIP) | Through-hole (DIP) |
| MSLレベル | Not applicable (through-hole hermetic ceramic) | — |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Technology | — | Bipolar EPROM, UV-erasable |
| Programmable Logic Elements | — | AND array + fixed OR array per macrocell |
| ピン数 | — | 24 |
| Programming Tool | — | Altera MAX+PLUS II / A+PLUS legacy |
| ライフサイクル状態 | — | Obsolete (mature legacy) |