EPM5032DC vs EPM5032DC-2 Vergleich
Detaillierter Direktvergleich von EPM5032DC von Altera und EPM5032DC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032DC | EPM5032DC-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,40 | $8,75 |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | 4 |
| Gehäuse | DIP-24 (ceramic, windowed) | 20-pin CDIP (Ceramic DIP) |
| Speed Grade | DC (commercial) | -2 (tPD ~25 ns, commercial) |
| Betriebstemperatur | 0C to +70C | 0C to +70C (commercial grade) |
| Technology | Bipolar EPROM, UV-erasable | — |
| Programmable Logic Elements | AND array + fixed OR array per macrocell | — |
| Configuration Memory | EPROM (UV-erasable via package window) | EPROM (one-time programmable per generation; UV-erasable variants exist) |
| Montageart | Through-hole (DIP) | Through-Hole (DIP) |
| Pin-Anzahl | 24 | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] |
| Programming Tool | Altera MAX+PLUS II / A+PLUS legacy | — |
| Lebenszyklusstatus | Obsolete (mature legacy) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | MAX 5000 |
| Usable Gates (typical) | — | 600 |
| Supply Voltage (VCC) | — | 5 V (single supply, +/-5%) |
| Programmable Pins / I/O | — | 20 pins (JEDEC-standard 0.300" ceramic DIP) |
| Programming Interface | — | Altera ByteBlaster / parallel-port JTAG-style ISP |
| Interconnect | — | Programmable Interconnect Array (PIA) with deterministic timing |
| MSL-Level | — | Not applicable (through-hole hermetic ceramic) |