EPM5064LI vs EPM5064JC Vergleich

Detaillierter Direktvergleich von EPM5064LI von Altera und EPM5064JC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5064LI EPM5064JC
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $7,10
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable PLD)
Macrocells 64 64
Logic Array Blocks (LABs) 4 —
Number of Terminals 44 —
Package Code QCCJ (PLCC-44, J-bend) —
Package Shape Square —
Configuration Memory UV-Erasable / OTP (EPROM-based) EPROM (UV-erasable window or OTP)
Supply Voltage (VCC) 4.5 V to 5.5 V 5 V (typical, 4.75 V - 5.25 V range)
Operating Temperature Grade Industrial —
Maximale Taktfrequenz 33.3 MHz —
Propagation Delay (tPD) 55 ns (typical) —
I/O Pins 28 bidirectional —
Dedicated Inputs 7 —
Total User Inputs 36 —
Process Technology 1-micron EPIC CMOS —
Latch-up Immunity 500 mA typical at 125 C —
Montageart Surface Mount Surface Mount (socketed)
RoHS-Status [DATA_NEEDED: confirm RoHS status - legacy Altera part] [DATA_NEEDED: RoHS compliance]
Usable Gates — 1,250 (approx.)
Logic Array Inputs — 36
Logic Array Outputs — 64
Gehäuse — 68-pin PLCC (JEDEC)
I/O Logic Level — TTL / CMOS compatible
Betriebstemperatur — [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL-Level — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

Datenblätter & Ressourcen

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