EPM5064LI vs EPM5064JC Comparison

Detailed side-by-side comparison of EPM5064LI by Altera and EPM5064JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064LI EPM5064JC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $7.10
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable PLD)
Macrocells 64 64
Logic Array Blocks (LABs) 4 β€”
Number of Terminals 44 β€”
Package Code QCCJ (PLCC-44, J-bend) β€”
Package Shape Square β€”
Configuration Memory UV-Erasable / OTP (EPROM-based) EPROM (UV-erasable window or OTP)
Supply Voltage (VCC) 4.5 V to 5.5 V 5 V (typical, 4.75 V - 5.25 V range)
Operating Temperature Grade Industrial β€”
Maximum Clock Frequency 33.3 MHz β€”
Propagation Delay (tPD) 55 ns (typical) β€”
I/O Pins 28 bidirectional β€”
Dedicated Inputs 7 β€”
Total User Inputs 36 β€”
Process Technology 1-micron EPIC CMOS β€”
Latch-up Immunity 500 mA typical at 125 C β€”
Mounting Type Surface Mount Surface Mount (socketed)
RoHS Status [DATA_NEEDED: confirm RoHS status - legacy Altera part] [DATA_NEEDED: RoHS compliance]
Usable Gates β€” 1,250 (approx.)
Logic Array Inputs β€” 36
Logic Array Outputs β€” 64
Package β€” 68-pin PLCC (JEDEC)
I/O Logic Level β€” TTL / CMOS compatible
Operating Temperature β€” [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) β€” [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) β€” [DATA_NEEDED: fCNT grade value]
Lead-Free β€” [DATA_NEEDED: lead-free status]
MSL Level β€” [DATA_NEEDED: MSL rating]
Programming Tool β€” Altera MAX+PLUS II / Quartus II (legacy device support)

Datasheets & Resources

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