EPM5128GC-2 vs EPM5128JC Vergleich
Detaillierter Direktvergleich von EPM5128GC-2 von Altera und EPM5128JC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5128GC-2 | EPM5128JC |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,95 | $9,75 |
| Family | MAX 5000 | — |
| Logic Elements / Gates | 2,500 usable gates | — |
| Macrocells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Maximum Operating Frequency | 50 MHz | — |
| Propagation Delay (tPD) | Approx. 25 ns (typical, -2 speed grade) | 35 ns |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (typical) |
| Package Type | 68-pin PGA (Pin Grid Array) | PLCC-68 (JLCC) ceramic, J-leaded |
| Package Code (per Partstack) | WPGA | — |
| Number of Terminals | 68 | — |
| Programming Technology | UV-erasable EPROM | — |
| Betriebstemperatur | 0C to +70C (commercial) | Commercial 0C to +70C |
| Grade (per Partstack) | COMMERCIAL | — |
| Terminal Form | PIN/PEG | — |
| Configuration Memory | Non-volatile, one-time programmable (erasable via UV) | UV-erasable EPROM (windowed package) |
| Product Family | — | MAX 5000 |
| Device Type | — | EPLD / CPLD |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Anzahl der Pins | — | 68 |
| Dedicated Inputs | — | 8 |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Montageart | — | Surface Mount (PLCC socket or solder) |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Process Technology | — | CMOS EPROM |
| RoHS-Status | — | [DATA_NEEDED: RoHS status - legacy part] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |