EPM5128GC-2 vs EPM5128JC 对比

详细并排对比 EPM5128GC-2 出自 Altera 和 EPM5128JC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5128GC-2 EPM5128JC
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $8.95 $9.75
Family MAX 5000 —
Logic Elements / Gates 2,500 usable gates —
Macrocells 128 —
Number of Usable Gates 2,500 —
Maximum Operating Frequency 50 MHz —
Propagation Delay (tPD) Approx. 25 ns (typical, -2 speed grade) 35 ns
Supply Voltage (VCC) 5 V (nominal) 5 V (typical)
Package Type 68-pin PGA (Pin Grid Array) PLCC-68 (JLCC) ceramic, J-leaded
Package Code (per Partstack) WPGA —
Number of Terminals 68 —
Programming Technology UV-erasable EPROM —
工作温度 0C to +70C (commercial) Commercial 0C to +70C
Grade (per Partstack) COMMERCIAL —
Terminal Form PIN/PEG —
Configuration Memory Non-volatile, one-time programmable (erasable via UV) UV-erasable EPROM (windowed package)
Product Family — MAX 5000
Device Type — EPLD / CPLD
Macrocell Count — 128
Logic Elements — Programmable AND/OR/XOR array
引脚数 — 68
Dedicated Inputs — 8
User I/O Pins — [DATA_NEEDED: user I/O pin count]
Programming Interface — Altera MAX+PLUS II / A+PLUS / legacy programmer
安装类型 — Surface Mount (PLCC socket or solder)
Boundary Scan — JTAG IEEE 1149.1 (family feature)
Process Technology — CMOS EPROM
RoHS 状态 — [DATA_NEEDED: RoHS status - legacy part]
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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