EPM5128GC2 vs EPM5128LC2 Vergleich
Detaillierter Direktvergleich von EPM5128GC2 von Altera und EPM5128LC2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera
EPM5128LC2 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM5128GC2 | EPM5128LC2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $54,00 | $22,40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Usable Gates | 2.5K | — |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | 8 |
| Maximum Internal Frequency | 50 MHz | — |
| Supply Voltage VCC | 5 V | — |
| I/O Pins | 64 | — |
| Dedicated Inputs | 16 | — |
| Gehäuse | Ceramic PGA (GC, windowed) | PGA (Pin Grid Array, ceramic) |
| Programmable Flip-Flop Modes | D / T / JK / SR (selectable) | — |
| Architecture | AND/OR plane + programmable macro cell + PIA | — |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Reprogrammability | UV-erasable (windowed ceramic package) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (extended commercial) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Configuration Memory | On-chip EPROM (no external boot device) | On-chip EPROM (non-volatile) |
| Pin-Anzahl | [DATA_NEEDED: total PGA pin count] | — |
| Macrocells | — | 128 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Global Clock Inputs | — | 1 dedicated |
| Propagation Delay (tPD) | — | 45 ns |
| Supply Voltage (VCC) | — | 5 V |
| Boundary Scan | — | JTAG / IEEE 1149.1 |
| Montageart | — | Through-Hole / Socketed |