EPM5128GC2 vs EPM5128LC2 对比

详细并排对比 EPM5128GC2 出自 Altera 和 EPM5128LC2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM5128LC2 EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera

EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera

EPM5128LC2 ⚠ 最后一次采购

规格对比

参数 EPM5128GC2 EPM5128LC2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $54.00 $22.40
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 128 —
Usable Gates 2.5K —
Logic Array Blocks (LABs) 8 (16 macro cells each) 8
Maximum Internal Frequency 50 MHz —
Supply Voltage VCC 5 V —
I/O Pins 64 —
Dedicated Inputs 16 —
封装 Ceramic PGA (GC, windowed) PGA (Pin Grid Array, ceramic)
Programmable Flip-Flop Modes D / T / JK / SR (selectable) —
Architecture AND/OR plane + programmable macro cell + PIA —
Process Technology CMOS EPROM CMOS EPROM
Reprogrammability UV-erasable (windowed ceramic package) —
工作温度 [DATA_NEEDED: operating temperature range] -40 C to +85 C (extended commercial)
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Configuration Memory On-chip EPROM (no external boot device) On-chip EPROM (non-volatile)
引脚数量 [DATA_NEEDED: total PGA pin count] —
Macrocells — 128
Interconnect — Programmable Interconnect Array (PIA)
Global Clock Inputs — 1 dedicated
Propagation Delay (tPD) — 45 ns
Supply Voltage (VCC) — 5 V
Boundary Scan — JTAG / IEEE 1149.1
安装类型 — Through-Hole / Socketed

数据手册与资源

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