EPM5128GC2 vs EPM5128LC2 Comparison
Detailed side-by-side comparison of EPM5128GC2 by Altera and EPM5128LC2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5128LC2
EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera
EPM5128LC2 β Last Time BuySpecification Comparison
| Parameter | EPM5128GC2 | EPM5128LC2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $54.00 | $22.40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | β |
| Usable Gates | 2.5K | β |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | 8 |
| Maximum Internal Frequency | 50 MHz | β |
| Supply Voltage VCC | 5 V | β |
| I/O Pins | 64 | β |
| Dedicated Inputs | 16 | β |
| Package | Ceramic PGA (GC, windowed) | PGA (Pin Grid Array, ceramic) |
| Programmable Flip-Flop Modes | D / T / JK / SR (selectable) | β |
| Architecture | AND/OR plane + programmable macro cell + PIA | β |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Reprogrammability | UV-erasable (windowed ceramic package) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (extended commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Configuration Memory | On-chip EPROM (no external boot device) | On-chip EPROM (non-volatile) |
| Pin Count | [DATA_NEEDED: total PGA pin count] | β |
| Macrocells | β | 128 |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Global Clock Inputs | β | 1 dedicated |
| Propagation Delay (tPD) | β | 45 ns |
| Supply Voltage (VCC) | β | 5 V |
| Boundary Scan | β | JTAG / IEEE 1149.1 |
| Mounting Type | β | Through-Hole / Socketed |