EPM5192ALC84-20 vs EPM5192AJC84-15 Vergleich

Detaillierter Direktvergleich von EPM5192ALC84-20 von Altera und EPM5192AJC84-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192ALC84-20 EPM5192AJC84-15
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $19,40 $18,95
Device Type UV-Erasable/OTP Complex PLD (EPLD) EPLD (Erasable Programmable Logic Device)
Series Altera MAX 5000 —
Macrocells 192 192
Process Technology CMOS CMOS EPROM
Speed Grade -20 (20 ns pin-to-pin delay) —
Gehäuse 84-pin PLCC (Plastic Leaded Chip Carrier) 84-pin PLCC (J84C) windowed ceramic
Terminal Pitch 1.270 mm —
Terminal Form J-bend —
Package Code QCCJ (PLCC-84) —
Package Shape Square —
Temperature Grade Commercial —
Programming Method UV-erase + EPROM (One-Time-Programmable option) UV-erase + EPROM programming (windowed package)
Logic Family MAX 5000 EPLD —
I/O Compatibility TTL-compatible —
Montageart Surface Mount (PLCC socket-compatible) Surface Mount
Configuration Memory EPROM (UV-erasable) —
RoHS-Status [DATA_NEEDED: RoHS status not in provided web data] Non-compliant (contains Pb, ceramic windowed package)
Family — MAX 5000
Propagation Delay (tpd) — 15 ns
Maximum Clock Frequency (fMAX) — 83.3 MHz
Supply Voltage (VCC) — 5 V (single supply)
Technology — CMOS, UV-erasable EPROM
Betriebstemperatur — [DATA_NEEDED: commercial/industrial/military grade]
Logic Blocks — 16 Logic Array Blocks (LABs)
I/O Pins — [DATA_NEEDED: user I/O count]

Datenblätter & Ressourcen

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