EPM5192ALC84-20 vs EPM5192AJC84-15 Comparaison
Comparaison détaillée côte à côte de EPM5192ALC84-20 par Altera et EPM5192AJC84-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoleteComparaison des spécifications
| Paramètre | EPM5192ALC84-20 | EPM5192AJC84-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $19,40 | $18,95 |
| Device Type | UV-Erasable/OTP Complex PLD (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Series | Altera MAX 5000 | — |
| Macrocells | 192 | 192 |
| Process Technology | CMOS | CMOS EPROM |
| Speed Grade | -20 (20 ns pin-to-pin delay) | — |
| Boîtier | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (J84C) windowed ceramic |
| Terminal Pitch | 1.270 mm | — |
| Terminal Form | J-bend | — |
| Package Code | QCCJ (PLCC-84) | — |
| Package Shape | Square | — |
| Temperature Grade | Commercial | — |
| Programming Method | UV-erase + EPROM (One-Time-Programmable option) | UV-erase + EPROM programming (windowed package) |
| Logic Family | MAX 5000 EPLD | — |
| I/O Compatibility | TTL-compatible | — |
| Type de montage | Surface Mount (PLCC socket-compatible) | Surface Mount |
| Configuration Memory | EPROM (UV-erasable) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status not in provided web data] | Non-compliant (contains Pb, ceramic windowed package) |
| Family | — | MAX 5000 |
| Propagation Delay (tpd) | — | 15 ns |
| Maximum Clock Frequency (fMAX) | — | 83.3 MHz |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Technology | — | CMOS, UV-erasable EPROM |
| Température de fonctionnement | — | [DATA_NEEDED: commercial/industrial/military grade] |
| Logic Blocks | — | 16 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: user I/O count] |