EPM5192ALC84-20 vs EPM5192AJC84-15 Comparación
Comparación detallada lado a lado de EPM5192ALC84-20 por Altera y EPM5192AJC84-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoleteComparación de especificaciones
| Parámetro | EPM5192ALC84-20 | EPM5192AJC84-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,40 | $18,95 |
| Device Type | UV-Erasable/OTP Complex PLD (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Series | Altera MAX 5000 | — |
| Macrocells | 192 | 192 |
| Process Technology | CMOS | CMOS EPROM |
| Speed Grade | -20 (20 ns pin-to-pin delay) | — |
| Encapsulado | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (J84C) windowed ceramic |
| Terminal Pitch | 1.270 mm | — |
| Terminal Form | J-bend | — |
| Package Code | QCCJ (PLCC-84) | — |
| Package Shape | Square | — |
| Temperature Grade | Commercial | — |
| Programming Method | UV-erase + EPROM (One-Time-Programmable option) | UV-erase + EPROM programming (windowed package) |
| Logic Family | MAX 5000 EPLD | — |
| I/O Compatibility | TTL-compatible | — |
| Tipo de montaje | Surface Mount (PLCC socket-compatible) | Surface Mount |
| Configuration Memory | EPROM (UV-erasable) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status not in provided web data] | Non-compliant (contains Pb, ceramic windowed package) |
| Family | — | MAX 5000 |
| Propagation Delay (tpd) | — | 15 ns |
| Maximum Clock Frequency (fMAX) | — | 83.3 MHz |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Technology | — | CMOS, UV-erasable EPROM |
| Temperatura de funcionamiento | — | [DATA_NEEDED: commercial/industrial/military grade] |
| Logic Blocks | — | 16 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: user I/O count] |