EPM5192AQM100-15 vs EPM5192AQM100-20 Vergleich

Detaillierter Direktvergleich von EPM5192AQM100-15 von Altera und EPM5192AQM100-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192AQM100-15 EPM5192AQM100-20
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $16,20 $8,20
Family MAX 5000 —
Device Type EPLD (Erasable PLD) —
Logic Array Blocks (LABs) 12 —
Interconnect Architecture Product Term Sharing (PIA) —
User I/O Pins 64 —
Dedicated Inputs 7 7
Total Inputs 72 —
Pin-to-Pin Delay (tPD) 25 ns —
Speed Grade -15 (15 ns macrocell delay) —
Gehäuse PQFP-100 (R-PQFP-G100) 100-pin PQFP (JESD-30 code R-PQFP-G100)
Process Technology CMOS CMOS EPROM-based
Programming Technology EPROM (UV-erasable) —
Versorgungsspannung 5 V (typical, single supply) [DATA_NEEDED: VCC range from datasheet]
Montageart Surface Mount Surface Mount
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: verified from manufacturer product page]
Betriebstemperatur [DATA_NEEDED: operating temperature range] —
Device Family — MAX 5000 (EPLD / classic CPLD)
Logic Elements — 192 macrocells across 12 Logic Array Blocks (LABs)
Number of LABs — 12
User I/O Lines — 64
Pin-to-Pin Propagation Delay (tPD) — 33 ns
Maximum Clock Frequency (fMAX) — 66.7 MHz
Configuration Memory — On-chip EPROM (non-volatile, one-time programmable in this package)
Boundary-Scan Test — JTAG / IEEE 1149.1 compatible
External Clock Input — Yes (global clock pin)
Operating Temperature Grade — [DATA_NEEDED: explicit temperature grade from datasheet]

Datenblätter & Ressourcen

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