EPM5192JC-2 vs EPM5192JC68 Vergleich
Detaillierter Direktvergleich von EPM5192JC-2 von Altera und EPM5192JC68 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JC-2 | EPM5192JC68 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $22,50 | $15,85 |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | UV-erasable Programmable Logic Device (PLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| User I/O Pins | 64 | 76 |
| Dedicated Inputs | 7 | 12 |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns | — |
| Maximale Taktfrequenz | 40 MHz | — |
| Process Technology | CMOS | — |
| Gehäuse | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | — |
| Montageart | Surface Mount | Surface Mount (PLCC socket compatible) |
| Number of Terminals | 84 | — |
| Programming Method | UV-erase / EPROM | — |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements / Macrocells | — | 192 macrocells |
| Anzahl der Pins | — | 68 |
| Package Type | — | PLCC-68 (J-Lead) |
| Betriebstemperatur | — | 0C to 70C (commercial, JC suffix) |
| Versorgungsspannung | — | [DATA_NEEDED: VCC] |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX] |
| Configuration Memory | — | UV-Erasable EPROM |
| Programmable Interconnect | — | Programmable Logic Array + Macrocells |
| Clock Pins | — | 4 dedicated |
| Programming Tool | — | MAX+PLUS II (legacy) |