EPM5192LC-2N vs EPM5192JC-1N Vergleich
Detaillierter Direktvergleich von EPM5192LC-2N von Altera und EPM5192JC-1N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LC-2N | EPM5192JC-1N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $11,85 | $19,85 |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Flip-Flops | 192 | — |
| Logic Elements | 192 macrocells (PAL/GAL-style AND-OR array) | — |
| Package Type | LC (ceramic J-leaded, windowed UV-erasable package family) | — |
| Speed Grade | -2 (tPD approximately 25 ns) | — |
| Propagation Delay (typical) | 25 ns | — |
| Versorgungsspannung | 5 V (typical) | — |
| Programmability | UV-erasable EPROM cell | — |
| Montageart | Surface Mount (LC package) | — |
| Betriebstemperatur | Commercial (0C to +70C) - inferred from speed-grade -2 designation | [DATA_NEEDED: industrial/commercial temperature range] |
| RoHS-Status | Compliant (per -N lead-free suffix) | — |
| Lead-Free | Yes (per -N suffix) | — |
| Architecture | Programmable Logic Array (PLA) with global PIA | — |
| Programming Interface | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) | JTAG / Altera ByteBlaster |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Logic Array Blocks (LABs) | — | 12 |
| Usable Gates | — | 3750 |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs (GCLK) | — | 1 |
| Propagation Delay (tPD) | — | 40 ns |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS EPROM (UV-erasable) |
| Gehäuse | — | 84-pin Ceramic Quad Flat Pack (CQFP) |
| JEDEC Package Code | — | S-CQCC-J84 |