EPM5192LC-2N vs EPM5192JC-1N 比較
詳細な並列比較: EPM5192LC-2N メーカー: Altera および EPM5192JC-1N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LC-2N | EPM5192JC-1N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $11.85 | $19.85 |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Flip-Flops | 192 | — |
| Logic Elements | 192 macrocells (PAL/GAL-style AND-OR array) | — |
| Package Type | LC (ceramic J-leaded, windowed UV-erasable package family) | — |
| Speed Grade | -2 (tPD approximately 25 ns) | — |
| Propagation Delay (typical) | 25 ns | — |
| 電源電圧 | 5 V (typical) | — |
| Programmability | UV-erasable EPROM cell | — |
| 実装タイプ | Surface Mount (LC package) | — |
| 動作温度 | Commercial (0C to +70C) - inferred from speed-grade -2 designation | [DATA_NEEDED: industrial/commercial temperature range] |
| RoHS ステータス | Compliant (per -N lead-free suffix) | — |
| Lead-Free | Yes (per -N suffix) | — |
| Architecture | Programmable Logic Array (PLA) with global PIA | — |
| Programming Interface | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) | JTAG / Altera ByteBlaster |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Logic Array Blocks (LABs) | — | 12 |
| Usable Gates | — | 3750 |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs (GCLK) | — | 1 |
| Propagation Delay (tPD) | — | 40 ns |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS EPROM (UV-erasable) |
| パッケージ | — | 84-pin Ceramic Quad Flat Pack (CQFP) |
| JEDEC Package Code | — | S-CQCC-J84 |