EPM5192LC-2N vs EPM5192JC-2 Vergleich

Detaillierter Direktvergleich von EPM5192LC-2N von Altera und EPM5192JC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LC-2N EPM5192JC-2
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $11,85 $22,50
Family MAX 5000 —
Macrocells 192 192
Flip-Flops 192 —
Logic Elements 192 macrocells (PAL/GAL-style AND-OR array) —
Package Type LC (ceramic J-leaded, windowed UV-erasable package family) —
Speed Grade -2 (tPD approximately 25 ns) —
Propagation Delay (typical) 25 ns —
Versorgungsspannung 5 V (typical) —
Programmability UV-erasable EPROM cell —
Montageart Surface Mount (LC package) Surface Mount
Betriebstemperatur Commercial (0C to +70C) - inferred from speed-grade -2 designation —
RoHS-Status Compliant (per -N lead-free suffix) [DATA_NEEDED: RoHS compliance]
Lead-Free Yes (per -N suffix) —
Architecture Programmable Logic Array (PLA) with global PIA —
Programming Interface Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) —
Device Family — MAX 5000
Product Type — UV-erasable Programmable Logic Device (PLD)
Logic Array Blocks (LABs) — 12
Interconnect — Programmable Interconnect Array (PIA)
User I/O Pins — 64
Dedicated Inputs — 7
External Clock Inputs — 1
Propagation Delay (tPD) — 45 ns
Maximale Taktfrequenz — 40 MHz
Process Technology — CMOS
Gehäuse — 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed)
Number of Terminals — 84
Programming Method — UV-erase / EPROM
Betriebstemperaturbereich — [DATA_NEEDED: operating temperature range]

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