EPM9320ALI84-10N vs EPM9320LI84-20N Vergleich
Detaillierter Direktvergleich von EPM9320ALI84-10N von Altera und EPM9320LI84-20N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320ALI84-10N | EPM9320LI84-20N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,95 | $9,75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | Multiple Array MatriX (MAX) - third generation |
| Process Technology | CMOS EEPROM | Advanced CMOS EEPROM |
| Usable Gates | 6,000 to 12,000 | 6,000 to 12,000 |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | — |
| User I/O Pins | 56 | 60 |
| Pin-to-Pin Delay | 10 ns | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | 144.9 MHz | 118 MHz |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| Gehäuse | 84-pin PLCC (J-lead, 1.270 mm pitch) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Montageart | Surface Mount (PLCC socket compatible) | — |
| Betriebstemperatur | -40C to +85C (industrial) | 0 C to +70 C (commercial) |
| Configuration Memory | EEPROM, non-volatile | — |
| Total Pins | — | 84 |
| Propagation Delay (tPD) | — | 20 ns (speed grade -20) |
| Logic Family | — | CMOS, EEPROM-based |
| Versorgungsspannung | — | 5.0 V |
| Programming Interface | — | IEEE 1149.1 JTAG, in-system programmable |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance status] |