EPM9320ALI84-10N vs EPM9320LI84-20N 비교
다음의 상세 나란히 비교: EPM9320ALI84-10N 제조: Altera 및 EPM9320LI84-20N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM9320ALI84-10N | EPM9320LI84-20N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $21.95 | $9.75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | Multiple Array MatriX (MAX) - third generation |
| Process Technology | CMOS EEPROM | Advanced CMOS EEPROM |
| Usable Gates | 6,000 to 12,000 | 6,000 to 12,000 |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | — |
| User I/O Pins | 56 | 60 |
| Pin-to-Pin Delay | 10 ns | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | 144.9 MHz | 118 MHz |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| 패키지 | 84-pin PLCC (J-lead, 1.270 mm pitch) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| 실장 유형 | Surface Mount (PLCC socket compatible) | — |
| 동작 온도 | -40C to +85C (industrial) | 0 C to +70 C (commercial) |
| Configuration Memory | EEPROM, non-volatile | — |
| Total Pins | — | 84 |
| Propagation Delay (tPD) | — | 20 ns (speed grade -20) |
| Logic Family | — | CMOS, EEPROM-based |
| 공급 전압 | — | 5.0 V |
| Programming Interface | — | IEEE 1149.1 JTAG, in-system programmable |
| RoHS 상태 | — | [DATA_NEEDED: RoHS compliance status] |