EPM9320ALI84-10N vs EPM9320LI84-20N Comparison
Detailed side-by-side comparison of EPM9320ALI84-10N by Altera and EPM9320LI84-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALI84-10N | EPM9320LI84-20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.95 | $9.75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | Multiple Array MatriX (MAX) - third generation |
| Process Technology | CMOS EEPROM | Advanced CMOS EEPROM |
| Usable Gates | 6,000 to 12,000 | 6,000 to 12,000 |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | β |
| User I/O Pins | 56 | 60 |
| Pin-to-Pin Delay | 10 ns | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | 144.9 MHz | 118 MHz |
| VCCINT (Core Supply) | 5.0 V | β |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | β |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | β |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | β |
| Package | 84-pin PLCC (J-lead, 1.270 mm pitch) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Mounting Type | Surface Mount (PLCC socket compatible) | β |
| Operating Temperature | -40C to +85C (industrial) | 0 C to +70 C (commercial) |
| Configuration Memory | EEPROM, non-volatile | β |
| Total Pins | β | 84 |
| Propagation Delay (tPD) | β | 20 ns (speed grade -20) |
| Logic Family | β | CMOS, EEPROM-based |
| Supply Voltage | β | 5.0 V |
| Programming Interface | β | IEEE 1149.1 JTAG, in-system programmable |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance status] |